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IMAGE SENSOR SOLUTIONS
Functional Description (continued)
11.0 DIGITAL VIDEO PORT
The captured image is placed onto a flexible 12-bit digital port as
shown in Figure 9. The digital video port consists of a program-
mable 12-bit digital Data Out Bus ( d[11:0] ) and three program-
This feature allows a programmable digital gain to be imple-
mented when connecting the sensor to 8 or 10 bit digital video
processing systems as illustrated in Figure 38. The unused bits
on the digital video bus can be optionally tri-stated.
mable synchronisation signals ( hsync, vsync, pclk ).
By default the synchronisation signals are configured to operate
in “ master” mode. They can be programed to operate in “ slave ”
mode.
The following sections are a detailed description of the timing
and programming modes of digital video port.
Pixel data is output on a 12-bit digital video bus. This bus can be
tri-stated by asserting the TriState bit in the VIDEOMODE1 reg-
ister.
KAC-
d11
d10
d9
d8
d7
d6
d5
d4
d3
d2
d1
d0
d9
d8
d7
d6
d5
d4
d3
d2
d1
d0
10 bit
Digital
Image
Processor
d8
d4
KAC-
11.1 Digital Video Data Out Bus (d[11:0])
A programmable matrix switch is provided to map the output of
the internal pixel framer to the pins of the digital video bus as
illustrated in Figure 37.
Internal Pixel Framer Output Register
11 10 9 8 7 6 5 4 3 2 1 0
d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
a) MSB Bit 11, Switch Mode (default)
Internal Pixel Framer Output Register
a) KAC-9627 Connected to a 10 bit Digital Image Processors
d11 d7
d10 d6
d9 d5
8 bit
d7 d3 Digital
d6 d2 Image
d5 d1 Processor
d4 d0
d3
d2
d1
d0
b) KAC-9627 Connected to a 8 bit Digital Image Processors
Figure 38. Example of connection to 10/8 bit systems
11 10
9
8
7
6
5
4
3
2
1
0
Synchronisation Signals in Master Mode
By default the sensor ’s digital video port’s synchronisation sig-
nals are configured to operate in master mode. In master mode
the integrated timing and control block controls the flow of data
onto the 12-bit digital port, three synchronisation outputs are
provided:
pclk
is the pixel clock output pin.
d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
b) MSB Bit 10, Switch Mode
hsync
vsync
is the horizontal synchronisation output signal.
is the vertical synchronisation output signal.
Internal Pixel Framer Output Register
11.2 Pixel Clock Output Pin (pclk) (Master Mode)
11 10
9
8
7
6
5
4
3
2
1
0
The pixel clock output pin, pclk, is provided to act as a synchro-
nisation reference for the pixel data appearing at the digital
video out bus pins d[11:0]. This pin can be programmed to oper-
ate in two modes:
? In free running mode the pixel clock output pin, pclk, is always
running with a fixed period. Pixel data appearing on the digital
video bus d[11:0] are synchronized to a specified active edge
d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
c) MSB bit 9, Switch Mode
Internal Pixel Framer Output Register
of the clock as shown in Figure 39.
pclk
d[11:0]
11 10
9
8
7
6
5
4
3
2
1
0
a) pclk active edge negative
pclk
d[11:0]
b) pclk active edge positive (default)
invalid pixel data
Figure 39. pclk in Free Running Mode
d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
d) MSB bit 8, Switch Mode
Figure 37. Digital Video Bus Switching Modes
? In data ready mode, the pixel clock output pin ( pclk ) will pro-
duce a pulse with a specified level every time valid pixel data
appears on the digital video bus d[11:0] as shown in Figure
40.
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22
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